1. Technical Field
This disclosure relates generally to logic circuits, and more particularly to a logic circuit family implementing self-resetting CMOS logic array macros for control logic.
2. Description of the Related Art
In fabricating microprocessor circuits, nearly all of the circuitry in current-generation microprocessors may be divided into dataflow devices, including execution units and their components, such as adders; into caches; and into control logic.
In particular, dataflow elements and caches share a number of characteristics:
1) Their logical descriptions are usually compact, with a ratio of logic statements to total transistors typically being under about 1:10,000 for an adder. PA1 2) Their regular logical structure allows repeated use of physical structures, which keeps the ratio of designed transistors to total transistors to a low value. PA1 3) The number of macros is limited; i.e. there are typically a few dozen macros with a size being of the same order of magnitude as a fixed-point unit adder. PA1 4) Dataflow and cache logical descriptions are established and fixed early in the project. PA1 1) Minimize the number of delay stages and parasitic loading on critical paths. PA1 2) Tune transistor widths to match their loads and required noise margins. PA1 3) Limit the number of global nodes in uncontrolled noise environments, requiring higher noise margins. PA1 4) Establish for local nodes a controlled low-noise environment, allowing lower noise margins. PA1 5) Use the best circuit techniques known, appropriate to the noise environment at each stage.
Because of these features, it is possible to hand-craft custom designs for dataflow and cache macros which are highly optimized at the level of individual transistors.
Control logic, on the other hand, generally has a much larger logical description which is typically random in nature, and is subject to revision by designers until the last possible moment in the schedule of the project. Control logic, therefore, requires a mostly automated design system with a rapid turn-around to provide a completely verified design for an individual macro, for example, in a matter of hours. At the same time, and partly due to the limitations of available automated design systems, control logic is an important limiting factor in the performance of processors heretofore known in the art, in which performance is measured, for example, by the multiplicative product of the clock frequency and the number of functions per clock cycle.
If one were to design a custom complementary metal oxide semiconductor (CMOS) circuit to perform a given function at high speed and at a reasonable cost in area and power, the following examples of general guidelines are to be adhered to:
Heretofore, control circuits have not been implementable by sufficiently rapid automated design techniques, and so any relatively quick turn-around has often resulted in excessive parasitics as well as noise figures exceeding specified noise margins.